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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4518 Dual synchronous BCD counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Dual synchronous BCD counter
FEATURES * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin compatible with the "4518" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4518 are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from
74HC/HCT4518
all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. APPLICATIONS * Multistage synchronous counting * Multistage asynchronous counting * Frequency dividers
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". propagation delay nCP0, nCP1 to nQn propagation delay nMR to nQn maximum clock frequency input capacitance power dissipation capacitance per counter notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 13 61 3.5 29 24 14 55 3.5 27 HCT ns ns MHz pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual synchronous BCD counter
PIN DESCRIPTION PIN NO. 1, 9 2, 10 3, 4, 5, 6 7, 15 8 11, 12, 13, 14 16 SYMBOL 1CP0, 2CP0 1CP1, 2CP1 1Q0 to 1Q3 1MR, 2MR GND 2Q0 to 2Q3 VCC NAME AND FUNCTION clock inputs (LOW-to-HIGH, edge-triggered) clock inputs (HIGH-to-LOW, edge-triggered) data outputs asynchronous master reset inputs (active HIGH) ground (0 V) data outputs positive supply voltage
74HC/HCT4518
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Dual synchronous BCD counter
FUNCTION TABLE nCP0 L X H X Notes nCP1 H X L X MR L L L L L L H
74HC/HCT4518
MODE counter advances counter advances no change no change no change no change Q0 to Q3 = LOW
Fig.4 Functional diagram.
1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990
4
Philips Semiconductors
Product specification
Dual synchronous BCD counter
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay nCP0, nCP1 to nQn propagation delay nMR to nQn output transition time 66 24 19 44 16 13 19 7 6 80 16 14 25 9 7 39 14 11 -22 -8 -6 22 8 6 18 55 66 -40 to +85 max. min. max. 210 42 36 150 30 26 75 15 13 100 20 17 150 30 26 0 0 0 100 20 17 4.8 24 28 265 53 45 190 38 33 95 19 16 120 24 20 180 36 31 0 0 0 120 24 20 4.0 20 24 -40 to +125 min. max. 315 63 59 225 45 38 110 22 19 ns
74HC/HCT4518
TEST CONDITIONS UNIT VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
WAVEFORMS
Fig.9
tPHL
ns
Fig.8
tTHL/ tTLH
ns
Fig.9
tW
clock pulse width HIGH or LOW
ns
Fig.8
tW
master reset pulse width 120 HIGH 24 20 removal time nMR to nCP0, nCP1 set-up time nCP1 to nCP0; nCP0 to nCP1 maximum clock pulse frequency nCP0, nCP1 0 0 0 80 16 14 6.0 30 35
ns
Fig.8
trem
ns
Fig.8
tsu
ns
Fig.7
fmax
MHz
Fig.8
December 1990
5
Philips Semiconductors
Product specification
Dual synchronous BCD counter
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT4518
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT nCP0, nCP1 nMR
UNIT LOAD COEFFICIENT 0.80 1.50
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem tsu propagation delay nCP0, nCP1 to nQn propagation delay nMR to nQn output transition time clock pulse width HIGH or LOW master reset pulse width HIGH removal time nMR to nCP0, nCP1 set-up time nCP1 to nCP0; nCP0 to nCP1 maximum clock pulse frequency nCP0, nCP1 20 20 0 16 28 17 7 11 11 -11 5 -40 to +85 max. min. max. 53 35 15 25 25 0 20 66 44 19 30 30 0 24 -40 to +125 min. max. 80 53 22 ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.9 Fig.8 Fig.9 Fig.8 Fig.8 Fig.8 Fig.7 UNIT V CC (V) WAVEFORMS TEST CONDITIONS
fmax
25
50
20
17
MHz
4.5
Fig.8
December 1990
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Philips Semiconductors
Product specification
Dual synchronous BCD counter
AC WAVEFORMS
74HC/HCT4518
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing hold and set-up times for nCP0 to nCP1 and nCP1 to nCP0.
Conditions: nCP1 = HIGH while nCP0 is triggered on a LOW-to-HIGH transition and nCP0 = LOW, while nCP1 is triggered on a HIGH-to-LOW transition. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the minimum pulse widths for nCP0, nCP1 and nMR inputs; the removal time for nMR and the propagation delay for nMR to nQn outputs and the maximum clock pulse frequency.
Conditions: nCP1 = HIGH while nCP0 is triggered on a LOW-to-HIGH transition and nCP0 = LOW, while nCP1 is triggered on a HIGH-to-LOW transition. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the propagation delays for nCP0, nCP1 to nQn outputs and the output transition times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7

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